1. Field of the Invention
The present invention relates to an appearance inspection apparatus and an appearance inspection method for carrying out an appearance inspection by processing a large amount of image data. More particularly, the present invention relates to a technique for processing the image data in parallel.
2. Description of the Related Art
Conventionally, an appearance inspection apparatus has been known for inspecting an appearance of an integrated circuit (IC) by processing image data generated by photographing the IC. As such an appearance inspection apparatus, for example, Japanese Laid Open Patent Application (JP-A-Heisei, 11-259434) discloses “Parallel Data Processor And Appearance Inspection Apparatus Including It” (hereafter, referred to as a first prior art). In this appearance inspection apparatus, a data input portion driven by a synchronous pulse from a drive signal bus receives image data and then transfers it through a data bus. A process distribution portion and processor elements monitor a state of the drive signal bus, and carries out a communication with each other through a communication bus in a pulse period, namely a high level period of the synchronous pulse.
The process distribution portion monitors a state of the processor elements, and assigns one processor element for processing unit image data to be transferred from the data input portion next in the pulse period of the synchronous pulse. The assigned processor element captures the unit image data from the data bus and processes the captured unit image data, and reports to be processing to the process distribution portion in the pulse period. When the processing is completed, the processor element reports to be waiting to the process distribution portion in a next synchronous pulse period. The above-mentioned configuration can improve an availability ratio of each processor element. Thus, especially, it is possible to attain a high-speed processing of data that is inputted continuously at a large amount, such as image data and the like.
Japanese Laid Open Patent Application (JP-A-Heisei, 11-135054) discloses “Charged Electron Beam Apparatus Having Parallel Image Processor” (hereafter, referred to as a second prior art). In this apparatus, a parallel image processor composed of one master CPU for controlling a data transfer and a plurality of slave CPUs for carrying out a data processing is equipped in an image-processing portion. A calculation program for image processing is downloaded from a control computer to the master CPU and the slave CPUs. The number of parallel image processors is variable. The optimal number of parallel CPUs is determined in advance, depending on a content of image processing. Also, a method of dividing an image data to be processed is variable and determined depending on a kind of image processing and a processing content. According to this apparatus, it is possible to execute not only a basic image processing but also image processing requiring an advanced calculation at a high speed.
Moreover, Japanese Laid Open Patent Application (JP-A-Heisei, 10-304184) discloses “Image Processing Apparatus And Image Processing Method” (hereafter, referred to as a third prior art). In this third prior art, division region data of image data is inputted to a plurality of division input devices. Then, image processing that can be independently processed for each division region is performed on each input division region data by using a pipeline process. The results of those pipeline processes are integrated.
These processes are executed under a control of a first integral-processing portion. That is, the first integral-processing portion issues a command to a pipeline to start the image processing. Also, the first integral processing-portion receives processed partial image data outputted from the pipeline, carries out a positioning operation, generates entire image data, and stores it in an image memory.
Also, for the sake of image processing which requires referring to a wide region, for example, such as a rotation of an image, it has a plurality of image processing portion and a second integral processing-portion for controlling them. This second integral processing-portion integrates the results processed by the plurality of image processors, and stores them in the image memory. The image processing at the high speed can be attained by executing the image processing independently performed for each division region and the image processing referring to the wide region at any order.
In the first prior art, every time the image data is inputted, the process distribution portion assigns the element processor. Thus, an overhead for the assignment is large to thereby impose a limitation on a high-speed processing. It is expected to require a process for integrating the results processed by the respective element processors, although this is not disclosed in detail.
In the second prior art, the slave CPUs are sequentially assigned under the control of the master CPU, similarly to the first prior art. The respective slave CPUs process the image data in parallel. Thus, this second prior art also has the problem similar to that of the first prior art.
In the third prior art, the first and second integral-processing portion carry out the operations, such as the start of the image processing, the integration of the processed image data and the like. Thus, the overhead is large to thereby result in the limitation on the high-speed processing of the image data. Also, it requires the two kinds, such as a section to carry out the image processing for each division region and a section to carry out the image processing for referring to the wide region. Hence, the configuration of the image processor is complex, and the size thereof is large.
Japanese Patent No. 2500649 discloses an IC extraneous material inspection apparatus that can detect an extraneous material such as mold fragment and fiber dust deposited between leads of IC.